With the repaid development of semiconductor manufacturing technologies, semiconductor devices have been developed toward higher device density and higher integration level. Transistors, as basic semiconductor devices, have been widely used. With the continuous increase of the device density and integration level, the channel length of a transistor has been continuously reduced. With the continuous reduction of the channel length of the transistor, the distance between the source and the drain of the transistor has been continuously reduced. Thus, the control ability of the gate of the transistor on the channel of the transistor has become weaker and weaker. Correspondingly, the sub-threshold leakage, i.e., the short-channel effect (SCE), is easy to occur; and the channel leakage current of the transistor is increased.
Thus, to better adapt the requirements for the miniaturization of semiconductor devices, semiconductor technologies have been gradually transferred from planar transistors to three-dimensional (3D) transistors which have better performance. A gate-all-around (GAA) transistor is one of the typical 3D transistors. In the GAA transistor, the gate surrounds all around the region having the channel. Comparing with a planar transistor, the control ability of the gate of the GAA transistor on the channel is greater; and the SCE of the transistor is better suppressed.
On the other hand, to increase the carrier mobility of the channel of a transistor, a stress layer is introduced to form the source region and the drain region of the transistor. By using the crystal lattice mismatch between the stress layer material and the channel material, the stress layer is able to apply a compressive stress or a tensile stress to the channel region of the transistor. Thus, the performance of the transistor is improved.
However, when the GAA structure is introduced into the transistor having the stress layer, the stress layer may be easily damaged. Accordingly, the performance of the semiconductor structure may be degraded. The disclosed methods and semiconductor structures are directed to solve one or more problems set forth above and other problems in the art.